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Features
* Single 2.7V - 3.6V Supply * Fast Read Access Time - 200 ns * Automatic Page Write Operation * * * * * * *
- Internal Address and Data Latches for 64 Bytes - Internal Control Timer Fast Write Cycle Times - Page Write Cycle Time: 10 ms Maximum - 1- to 64-byte Page Write Operation Low Power Dissipation - 15 mA Active Current - 20 A CMOS Standby Current Hardware and Software Data Protection DATA Polling for End of Write Detection High Reliability CMOS Technology - Endurance: 10,000 Cycles - Data Retention: 10 Years JEDEC Approved Byte-wide Pinout Commercial and Industrial Temperature Ranges
256K (32K x 8) Battery-VoltageTM Parallel EEPROMs AT28BV256
Description
The AT28BV256 is a high-performance Electrically Erasable and Programmable Read Only Memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufactured with Atmel's advanced nonvolatile CMOS technology, the device offers access times to 200 ns with power dissipation of just 54 mW. When the device is deselected, the CMOS standby current is less than 200 A. (continued)
Pin Configurations
Pin Name A0 - A14 CE OE WE I/O0 - I/O7 NC DC Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs No Connect Don't Connect PLCC Top View
A7 A12 A14 DC VCC WE A13
PDIP, SOIC Top View
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
TSOP Top View
A8 A9 A11 NC OE A10 CE I/O7 I/O6 OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2
I/O1 I/O2 GND DC I/O3 I/O4 I/O5
14 15 16 17 18 19 20
A6 A5 A4 A3 A2 A1 A0 NC I/O0
5 6 7 8 9 10 11 12 13
4 3 2 1 32 31 30
29 28 27 26 25 24 23 22 21
Rev. 0273G-11/99
Note: PLCC package pins 1 and 17 are DON'T CONNECT.
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The AT28BV256 is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 64-byte page register to allow writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to 64 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA polling
of I/O7. Once the end of a write cycle has been detected a new access for a read or write can begin. Atmel's 28BV256 has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protection mechanism is available to guard against inadvertent writes. The device also includes an extra 64 bytes of EEPROM for device identification or tracking.
Block Diagram
Absolute Maximum Ratings*
Temperature under Bias ................................ -55C to +125C Storage Temperature ..................................... -65C to +150C All Input Voltages (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V Voltage on OE and A9 with Respect to Ground ...................................-0.6V to +13.5V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability
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AT28BV256
AT28BV256
Device Operation
READ: The AT28BV256 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE or OE is high. This dualline control gives designers flexibility in preventing bus contention in their system. BYTE WRITE: A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started it will automatically time itself to completion. Once a programming operation has been initiated and for the duration of t WC , a read operation will effectively be a polling operation. PAGE WRITE: The page write operation of the AT28BV256 allows 1 to 64 bytes of data to be written into the device during a single internal programming period. A page write operation is initiated in the same manner as a byte write; the first byte written can then be followed by 1 to 63 additional bytes. Each successive byte must be written within 150 s (tBLC) of the previous byte. If the tBLC limit is exceeded the AT28BV256 will cease accepting data and commence the internal programming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A6 - A14 inputs. For each WE high to low transition during the page write operation, A6 - A14 must be the same. The A0 to A5 inputs are used to specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur. DATA POLLING: The AT28BV256 features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. DATA Polling may begin at anytime during the write cycle. TOGGLE BIT: In addition to DATA Polling the AT28BV256 provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop toggling and valid data will be read. Reading the toggle bit may begin at any time during the write cycle. DATA PROTECTION: If precautions are not taken, inadvertent writes may occur during transitions of the host system power supply. Atmel has incorporated both hardware and software features that will protect the memory against inadvertent writes. HARDWARE PROTECTION: Hardware features protect against inadvertent writes to the AT28BV256 in the following ways: (a) VCC power-on delay--once VCC has reached 1.8V (typical) the device will automatically time out 10 ms (typical) before allowing a write; (b) write inhibit--holding any one of OE low, CE high or WE high inhibits write cycles; and (c) noise filter--pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a write cycle. SOFTWARE DATA PROTECTION: A software-controlled data protection feature has been implemented on the AT28BV256. Software data protection (SDP) helps prevent inadvertent writes from corrupting the data in the device. SDP can prevent inadvertent writes during power-up and power-down as well as any other potential periods of system instability. The AT28BV256 can only be written using the software data protection feature. A series of three write commands to specific addresses with specific data must be presented to the device before writing in the byte or page mode. The same three write commands must begin each write operation. All software write commands must obey the page mode write timing specifications. The data in the 3-byte command sequence is not written to the device; the address in the command sequence can be utilized just like any other location in the device. Any attempt to write to the device without the 3-byte sequence will start the internal write timers. No data will be written to the device; however, for the duration of tWC, read operations will effectively be polling operations. DEVICE IDENTIFICATION: An extra 64 bytes of EEPROM memory are available to the user for device identification. By raising A9 to 12V 0.5V and using address locations 7FC0H to 7FFFH the additional bytes may be written to or read from in the same manner as the regular memory array.
3
DC and AC Operating Range
AT28BV256-20 Operating Temperature (Case) VCC Power Supply Com. Ind. 0C - 70C -40C - 85C 2.7V - 3.6V AT28BV256-25 0C - 70C -40C - 85C 2.7V - 3.6V
Operating Modes
Mode Read Write
(2)
CE VIL VIL VIH X X X VIL
OE VIL VIH X
(1)
WE VIH VIL X VIH X X VIL
I/O DOUT DIN High Z
Standby/Write Inhibit Write Inhibit Write Inhibit Output Disable Chip Erase Notes: 1. X can be VIL or VIH. 2. Refer to AC programming waveforms. 3. VH = 12.0V 0.5V.
X VIL VIH VH
(3)
High Z High Z
DC Characteristics
Symbol ILI ILO ISB ICC VIL VIH VOL VOH Parameter Input Load Current Output Leakage Current VCC Standby Current CMOS VCC Active Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 1.6 mA IOH = -100 A 2.0 2.0 0.3 Condition VIN = 0V to VCC + 1V VI/O = 0V to VCC Com. CE = VCC - 0.3V to VCC + 1V f = 5 MHz; IOUT = 0 mA Ind. Min Max 10 10 20 50 15 0.6 Units A A A A mA V V V V
4
AT28BV256
AT28BV256
AC Read Characteristics
AT28BV256-20 Symbol tACC tCE
(1) (2)
AT28BV256-25 Min Max 250 250 0 0 0 100 60 Units ns ns ns ns ns
Parameter Address to Output Delay CE to Output Delay OE to Output Delay CE or OE to Output Float Output Hold from OE, CE or Address, whichever occurred first
Min
Max 200 200
tOE tDF
0 0 0
80 55
(3)(4)
tOH
AC Read Waveforms(1)(2)(3)(4)
tCE tOE tDF tACC tOH
Notes:
1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. 3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and Measurement Level
Output Test Load
tR, tF < 20 ns
Pin Capacitance
f = 1 MHz, T = 25C(1)
Symbol CIN COUT Note: Typ 4 8 Max 6 12 Units pF pF Conditions VIN = 0V VOUT = 0V
1. This parameter is characterized and is not 100% tested.
5
AC Write Characteristics
Symbol tAS, tOES tAH tCS tCH tWP tDS tDH, tOEH tDV Note: Parameter Address, OE Set-up Time Address Hold Time Chip Select Set-up Time Chip Select Hold Time Write Pulse Width (WE or CE) Data Set-up Time Data, OE Hold Time Time to Data Valid 1. NR = No Restriction. Min 0 50 0 0 200 50 0 NR
(1)
Max
Units ns ns ns ns ns ns ns
AC Write Waveforms
WE Controlled
tOES tOEH
tAS
tAH
tCH
tCS tWPH tWP tDV tDS tDH
CE Controlled
tOES tOEH
tAS
tAH
tCH
tCS tWPH tWP tDV tDS tDH
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AT28BV256
AT28BV256
Page Mode Characteristics
Symbol tWC tAS tAH tDS tDH tWP tBLC tWPH Parameter Write Cycle Time Address Set-up Time Address Hold Time Data Set-up Time Data Hold Time Write Pulse Width Byte Load Cycle Time Write Pulse Width High 100 0 50 50 0 200 150 Min Max 10 Units ms ns ns ns ns ns s ns
Programming Algorithm
LOAD DATA AA TO ADDRESS 5555
Notes for software program code: 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). 2. 3. Data protect state will be re-activated at the end of program cycle. 1 to 64 bytes of data are loaded.
LOAD DATA 55 TO ADDRESS 2AAA
LOAD DATA A0 TO ADDRESS 5555
WRITES ENABLED(2)
LOAD DATA XX TO ANY ADDRESS(3)
LOAD LAST BYTE TO LAST ADDRESS(3)
ENTER DATA PROTECT STATE
Software Protected Program Cycle Waveforms(1)(2)(3)
tWP tAS tAH
tWPH tDH
tBLC
tDS
tWC
Notes:
1. 2. 3.
A0 - A14 must conform to the addressing sequence for the first three bytes as shown above. A6 through A14 must specify the same page address during each high to low transition of WE (or CE) after the software code has been entered. OE must be high only when WE and CE are both low.
7
DATA Polling Characteristics(1)
Symbol tDH tOEH tOE tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay
(2)
Min 0 0
Typ
Max
Units ns ns ns
Write Recovery Time 1. These parameters are characterized and not 100% tested. 2. See "AC Read Characteristics" on page 5.
0
ns
DATA Polling Waveforms
tOEH tDH tOE tWR
Toggle Bit Characteristics(1)
Symbol tDH tOEH tOE tOEHP tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay OE High Pulse Write Recovery Time 1. These parameters are characterized and not 100% tested. 2. See "AC Read Characteristics" on page 5.
(2)
Min 10 10
Typ
Max
Units ns ns ns
150 0
ns ns
Toggle Bit Waveforms
tOEH tDH tOE tWR
Notes: 1. 2. 3. Toggling either OE or CE or both OE and CE will operate toggle bit. Beginning and ending state of I/O6 will vary. Any address location may be used but the address should not vary.
8
AT28BV256
AT28BV256
9
Ordering Information(1)
tACC (ns) 200 ICC (mA) Active 15 Standby 0.02 Ordering Code AT28BV256-20JC AT28BV256-20PC AT28BV256-20SC AT28BV256-20TC AT28BV256-20JI AT28BV256-20PI AT28BV256-20SI AT28BV256-20TI AT28BV256-25JC AT28BV256-25PC AT28BV256-20SC AT28BV256-25TC AT28BV256-25JI AT28BV256-25PI AT28BV256-20SI AT28BV256-25TI Package 32J 28P6 28S 28T 32J 28P6 28S 28T 32J 28P6 28S 28T 32J 28P6 28S 28T Operation Range Commercial (0 to 70C)
15
0.02
Industrial (-40 to 85C)
250
15
0.02
Commercial (0 to 70C)
15
0.02
Industrial (-40 to 85C)
Note:
1. See Valid Part Numbers table below.
Valid Part Numbers
The following table lists standard Atmel products that can be ordered.
Device Numbers AT28BV256 AT28BV256 Speed 20 25 Package and Temperature Combinations JC, JI, PC, PI, SC, SI, TC, TI JC, JI, PC, PI, SC, SI, TC, TI
Die Products
Reference Section: Parallel EEPROM Die Products
Package Type 32J 28P6 28S 28T 32-lead, Plastic J-leaded Chip Carrier (PLCC) 28-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 28-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) 28-lead, Plastic Thin Small Outline Package (TSOP)
10
AT28BV256
AT28BV256
Packaging Information
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-016 AE
28P6, 28-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-011 AB
.045(1.14) X 45
PIN NO. 1 IDENTIFY
.025(.635) X 30 - 45 .012(.305) .008(.203) .530(13.5) .490(12.4) .021(.533) .013(.330) .030(.762) .015(.381) .095(2.41) .060(1.52) .140(3.56) .120(3.05)
1.47(37.3) 1.44(36.6)
PIN 1
.032(.813) .026(.660)
.553(14.0) .547(13.9) .595(15.1) .585(14.9)
.566(14.4) .530(13.5)
.050(1.27) TYP
1.300(33.02) REF .220(5.59) MAX SEATING PLANE .161(4.09) .125(3.18) .110(2.79) .090(2.29) .065(1.65) .041(1.04) .630(16.0) .590(15.0) 0 REF 15 .690(17.5) .610(15.5)
.090(2.29) MAX .005(.127) MIN
.300(7.62) REF .430(10.9) .390(9.90) AT CONTACT POINTS
.065(1.65) .015(.381) .022(.559) .014(.356)
.022(.559) X 45 MAX (3X) .453(11.5) .447(11.4) .495(12.6) .485(12.3)
.012(.305) .008(.203)
28S, 28-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) Dimensions in Inches and (Millimeters)
28T, 28-lead, Plastic Thin Small Outline Package (TSOP) Dimensions in Millimeters and (Inches)*
INDEX MARK AREA 11.9 (0.469) 11.7 (0.461) 13.7 (0.539) 13.1 (0.516)
0.55 (0.022) BSC 7.15 (0.281) REF 8.10 (0.319) 7.90 (0.311)
0.27 (0.011) 0.18 (0.007)
1.25 (0.049) 1.05 (0.041)
0.20 (0.008) 0.10 (0.004) 0 5 REF 0.20 (0.008) 0.15 (0.006)
0.70 (0.028) 0.30 (0.012)
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(c) Atmel Corporation 1999. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life suppor t devices or systems. Marks bearing
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